Tensilica Uses Synopsys Design Compiler FPGA Tool to Improve Prototyping Design Flow
SANTA CLARA, Calif.—(BUSINESS WIRE)—Jan. 12, 2005—
Tensilica, Inc., the leading supplier of configurable
and extensible microprocessor cores, announced that it has based its
FPGA prototyping design flow on the Design Compiler(R) FPGA (DC FPGA)
tool from Synopsys, Inc. Only DC FPGA supports key design elements of
the Tensilica(R) processor. When designers of Tensilica's Xtensa(R)
configurable processors want to create an FPGA-based prototype of a
system on chip (SoC) that incorporates one or more Xtensa processors
before committing to final silicon, Tensilica's patented Xtensa
Processor Generator uses the DC FPGA tool to generate an optimized
FPGA netlist.
"The DC FPGA tool is the only FPGA synthesis solution that
supports key design elements of our Xtensa LX processor, including
fine-grain clock gating," stated Ashish Dixit, vice president of
Engineering for Tensilica. "Design teams that use Tensilica's Xtensa
LX processor and DC FPGA achieve better quality-of-results, faster
time to prototype and lower prototype costs."
Since designers can extensively customize Xtensa processors, many
design teams download different configurations into FPGA-based
emulation platforms to test the complete SoC including the
custom-configured processor. The Xtensa Processor Generator uses the
DC FPGA tool to quickly deliver optimized versions of these customized
configurations as pre-verified FPGA netlists.
Highly efficient implementations and maximum system performance
are obtained by taking advantage of the unique fine-grain clock gating
transformations and register retiming capabilities in the DC FPGA
tool. The fine-grain clock gating transformations map complex register
control logic into a highly efficient implementation tailored to the
specific FPGA device to be used as the prototype. The register
retiming relies on the DC FPGA tool to insert registers in complex
multi-cycle logic to maximize system performance.
"Tensilica has discovered the value of applying the Design
Compiler compatible flow for prototyping ASICs on FPGAs," said Michael
Jackson, vice president of Engineering, ASIC and FPGA Synthesis, at
Synopsys. "Use of Design Compiler FPGA to prototype customized Xtensa
processors allows designers to evaluate a broad range of
implementations before selecting the one for their ASIC, leading to
products that more closely meet their cost, functionality, and
performance goals."
About Tensilica
Tensilica was founded in July 1997 to address the growing need for
optimized, application-specific microprocessor solutions in
high-volume embedded applications. With a configurable and extensible
microprocessor core called Xtensa, Tensilica is the only company that
has automated and patented the time-consuming process of generating a
customized microprocessor core along with a complete software
development tool environment, producing new configurations in a matter
of hours. For more information, visit www.tensilica.com.
Editors' Notes
-- Tensilica and Xtensa are registered trademarks belonging to
Tensilica Inc. All other company and product names are
trademarks and/or registered trademarks of their respective
owners.
-- Tensilica's announced licensees include Agilent, ALPS, AMCC
(JNI Corporation), Astute Networks, ATI, Avision, Bay
Microsystems, Berkeley Wireless Research Center, Broadcom,
Cisco Systems, Conexant Systems, Cypress, Crimson
Microsystems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd.,
Hudson Soft, Hughes Network Systems, Ikanos Communications, LG
Electronics, Marvell, NEC Laboratories America, NEC
Corporation, NetEffect, Nippon Telephone and Telegraph (NTT),
Olympus Optical Co. Ltd., S2io, Solid State Systems, Sony,
STMicroelectronics, Stretch, TranSwitch Corporation, and
Victor Company of Japan (JVC).
Contact:
Tensilica, Inc.
Paula Jones, 408-327-7343
paula@tensilica.com
or
Tanis Communications, Inc.
Joany Draeger, 650-365-3395
joany@taniscomm.com
